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Primary, copy A
Task A
1. After receiving a request, the controller performs four DMA transfers. These
transfers write the alternate data structure for task A.
2. The controller performs task A.
3. After the controller completes the task it enters the arbitration process.
After the peripheral issues a new request and it has the highest priority then the process continues with:
Primary, copy B
Task B
4. The controller performs four DMA transfers. These transfers write the alternate
data structure for task B.
5. The controller performs task B. To enable the controller to complete the task,
the peripheral must issue a further three requests.
6. After the controller completes the task it enters the arbitration process.
After the peripheral issues a new request and it has the highest priority then the process continues with:
Primary, copy C
Task C
7. The controller performs four DMA transfers. These transfers write the alternate
data structure for task C.
8. The controller performs task C.
9. After the controller completes the task it enters the arbitration process.
After the peripheral issues a new request and it has the highest priority then the process continues with:
Primary, copy D
Task D
10.The controller performs four DMA transfers. These transfers write the alternate
data structure for task D.
11.The controller sets the cycle_ctrl bits of the primary data structure to b000, to
indicate that this data structure is now invalid.
12.The controller performs task D using a basic cycle.
13.The controller sets dma_done[C] HIGH for one HFCORECLK cycle and enters
the arbitration process.
8.4.2.4 Error signaling
If the controller detects an ERROR response on the AHB-Lite master interface, it:
? disables the channel that corresponds to the ERROR
? sets dma_err HIGH.
After the host processor detects that dma_err is HIGH, it must check which channel was active when
the ERROR occurred. It can do this by:
1. Reading the DMA_CHENS register to create a list of disabled channels.
When a channel asserts dma_done[ ] then the controller disables the channel. The program running
on the host processor must always keep a record of which channels have recently asserted their
dma_done[ ] outputs.
2. It must compare the disabled channels list from step 1 (p. 50) , with the record of the channels that
have recently set their dma_done[ ] outputs. The channel with no record of dma_done[C] being
set is the channel that the ERROR occurred on.
8.4.3 Channel control data structure
You must provide an area of system memory to contain the channel control data structure. This system
memory must:
2011-04-12 - d0001_Rev1.10
50
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